In recent years, with increase of functions of television receivers and enhancement of the image quality, a digital video signal processing technology has been more and more utilized, and accordingly greater importance has been put on video signal processors that can make video signals to be synchronized with various clock signals.
Hereinafter, a conventional video signal processor will be described with reference to FIG. 8. FIG. 8 is a block diagram schematically illustrating a structure of a conventional video signal processor.
In FIG. 8, a video data signal S100 including video data is inputted to this video signal processor through a video signal input terminal 100. A first clock signal S101 is inputted through a clock input terminal 101. A second clock signal S102 is inputted through a clock input terminal 102. A reference signal S103 indicating a start position of screen display, such as a horizontal sync signal, is inputted through a reference signal input terminal 103.
In FIG. 8, delay elements 104 to 107 can vary respective delay values. When control of the delay values (which will be described later) is completed, the delay element 104 phase shifts the second clock signal S102 by ¼ clock (i.e., one-fourth of the period of the clock), and the delay elements 105, 106, and 107 each phase shift a delayed clock from the immediately preceding delay element by ¼ clock. A selector 108a selects a delayed clock that is the most synchronized with the reference signal S103 from among the delayed clocks S104 to S107 which have been delayed by the respective delay elements 104 to 107, and outputs the selected clock as a second clock signal S108a. A phase comparator 112 compares phases between a clock that is obtained by delaying a focus clock in the second clock signal S102 by one clock using the delay elements 104 to 107, and a clock that is one clock later than the focus clock. A control circuit 113 outputs a control signal S113 for controlling the respective delay values of the delay elements 104 to 107 on the basis of a phase difference output S112 from the phase comparator 112.
In FIG. 8, a memory 110a utilizes the first clock signal S101 for writing a video data signal S100 and the second clock signal S108a for reading an output video data signal S110a. The output video data signal S110a is outputted through a video signal output terminal 114, and the second clock signal S108a is outputted through a clock output terminal 115.
The operation of the conventional video signal processor that is constructed as described above will be described.
When the video data signal S100 including video data is inputted through the video signal input terminal 100 and the first clock signal S101 is inputted through the clock input terminal 101, the video data are stored in the memory 110a in accordance with the first clock signal S101.
The second clock signal S102 inputted through the clock input terminal 102 is delayed successively by ¼ clock, by the delay elements 104 to 107, respectively.
The delayed clock S107 is inputted from the delay element 107 to the phase comparator 112 as a comparison signal, and a clock that is one clock later than the clock inputted through the clock input terminal 102 is inputted to the phase comparator 112 as a signal to be compared with the comparison signal (hereinafter, referred to as a to-be-compared signal). The phase comparator 112 compares the phases between the comparison signal and the to-be-compared signal, thereby detecting a phase difference, and outputs a phase difference output S112 to the control circuit 113. The control circuit 113 outputs a control signal S113 for controlling the respective delay values of the delay elements 104 to 107 on the basis of the phase difference output S112.
When this operation for controlling the respective delay values of the delay elements 104 to 107 on the basis of the phase difference between the delayed clock S107 that is obtained by delaying the second clock signal S102 by one clock and the clock that is one clock later than the second clock signal S102 is repeatedly performed until the phase comparator 112 detects no phase difference, the delay values of the delay elements 104 to 107 become approximately the same. At this time, the respective delay elements 104 to 107 output the delayed clocks S104 to S107 which are obtained by delaying the second clock signal S102 successively by ¼ clock.
These delayed clocks S104 to S107 which are phase shifted with each other by ¼ clock are inputted to the selector 108a, respectively. The selector 108a selects one of the delayed clocks S104 to S107, which is the most synchronized with the reference signal S103 inputted through the reference signal input terminal 103, and supplies the selected delayed clock to the memory 110a as a second clock signal S108a as well as outputs the same through the clock output terminal 115.
On the other hand, the video data written in the memory 110a are read as an output video data signal S110a in accordance with the second clock signal S108a, and outputted through the video signal output terminal 114. At this time, the clock for the output video data signal S110a is switched from the first clock signal S101 to the second clock signal S108a that is in phase with the reference signal S103. (See Japanese Published Patent Application No. 2002-290218, pp. 7-10, FIGS. 1, 2)
However, since the conventional video signal processor changes the clock so as to be in phase with the reference signal, the length of one period of the clock varies at the changing. For example, as shown in FIG. 9, when the clock is switched from clock CK2 to clock CK1, the period of the clock is shortened at the changing. When one period of the clock becomes a length that is not within a specified range or when the period of the clock is shortened, an arithmetic error may occur in the video signal processor, or an arithmetic unit that is connected at a later stage of the video signal processor and utilizes the second clock signal S108a outputted from the clock output terminal 115, resulting in disturbances in a displayed picture or malfunction of the apparatus.